Various types of non-volatile memory devices employ materials that can be caused to selectively exhibit more than one stable value of electrical resistivity. To form a single memory cell (i.e., one bit), a volume of such a material may be provided between two electrodes. A selected voltage (or current) may be applied between the electrodes, and the resulting electrical current (or voltage) therebetween will be at least partially a function of the particular value of the electrical resistivity exhibited by the material between the electrodes. A relatively higher electrical resistivity may be used to represent a “1” in binary code, and a relatively low electrical resistivity may be used to represent a “0” in binary code, or vice versa. By selectively causing the material between the electrodes to exhibit relatively high and low values of electrical resistivity, the memory cell can be selectively characterized as exhibiting either a 1 or a 0 value.
One particular type of such non-volatile memory devices is a phase change memory device. In a phase change memory cell, the material provided between the electrodes is capable of exhibiting at least two microstructural phases or states, each of which exhibits a different value of electrical resistivity. For example, the so-called “phase change material” may be capable of existing in a crystalline phase (i.e., the atoms of the material exhibit relative long range order) and an amorphous phase (i.e., the atoms of the material do not exhibit any or relatively little long range order). Typically, the amorphous phase is formed by heating at least a portion of the phase change material to a temperature above the melting point thereof, and then rapidly cooling the phase change material to cause the material to solidify before the atoms thereof can assume any long range order. To transform the phase change material from the amorphous phase to a crystalline phase, the phase change material is typically heated to an elevated temperature below the melting point, but above a crystallization temperature, for a time sufficient to allow the atoms of the material to assume the relatively long range order associated with the crystalline phase. For example, Ge2Sb2Te5 (often referred to as “GST”) is often used as a phase change material. This material has a melting point of about 600° C., and is capable of existing in amorphous and crystalline states. To form the amorphous (high resistivity) phase, at least a portion of the material is heated to a temperature above the melting point thereof by applying a relatively high current through the material between the electrodes (the heat being generated due to the electrical resistance of the phase change material) for as little as 10 nanoseconds to 100 nanoseconds. As the GST material quickly cools when the current is interrupted, the atoms of the GST do not have sufficient time to form an ordered crystalline state, and the amorphous phase of the GST material is formed. To form the crystalline (low resistivity) phase, at least a portion of the material may be heated to a temperature of above 400° C., which is above the crystallization temperature and near, but below, the melting point of the GST material, by applying a relatively lower current through the GST material between the electrodes for a sufficient amount of time (e.g., as little as about 30 nanoseconds) to allow the atoms of the GST material to assume the long range order associated with the crystalline phase, after which the current flowing through the material may be interrupted. The current passed through the phase change material to cause a phase change therein may be referred to as the “programming current.”
Various memory devices having memory cells comprising variable resistance material, as well as methods for forming such memory devices and using such memory devices are known in the art. For example, memory cells comprising variable resistance materials and methods of forming such memory cells are disclosed in U.S. Pat. No. 6,150,253 to Doan et al., U.S. Pat. No. 6,294,452, U.S. Pat. No. 7,057,923 to Furkay et al., U.S. Pat. No. 7,518,007 to Seo et al., United States Patent Application Publication No. 2006/0034116 A1 to Lam et al., and United States Patent Application Publication No. 2006/0152186 A1 to Suh et al. Furthermore, supporting circuitry that may be used to form a memory device comprising memory cells having a variable resistance material, as well as methods of operating such memory devices, are disclosed in, for example, U.S. Pat. No. 6,885,602 to Cho et al., U.S. Pat. No. 7,050,328 to Khouri et al., and U.S. Pat. No. 7,130,214 to Lee.